Improving Cache Utilization of Linear Relaxation Methods: Theory and Practice

Applic~atiori codes wliilblg ac,hievr performance f;lr Itw than tht, iidvertist~tl c,apabilities of cxistiug archit,tytnrcs, and this pmble~ii is worsening with irlc,reasingly-I)arallcl machines. For large-scale nunlorical ilpplic~at,iorls, stencil opcratioris oftm iiriposc the grcat,cr part of the wmputat,ional cost, ant1 the primary sources of incfficic3icy arc thr costs of lllrssagc passing and poor c~he utilizat,ion. This paper proposes ant1 dcmonstjratcs optirnizations for stencil imd stencil-like comput,ations fol bot,li x2-ial ant1 parallel enviroriIrit,iit,s t,hat arr~eliorat,e tliesc sources of iw cfficienc~. Xtltlitiodly, we ;trgue that when stencil-like wmput,ations arc enc:odctl ;lt il high low1 using ob~cc,t-oricntt,d parallel array class libr;irics, thcw optinlizations, which arc hyo~~tl the capability of coxlpilcrs, rua>